The present invention generally relates to decoding circuits, and more particularly to a decoding circuit for decoding an input code into a first predetermined number of high-level outputs and a second predetermined number of low-level outputs.
As will be described later in the present specification in conjunction with a drawing, a first conventional decoding circuit comprises a decoding part and a distributing part. With respect to a 2-bit input code, for example, the decoding part comprises four 2-input NAND gates, and the distributing part comprises a 4-input NAND gate, a 3-input NAND gate, a 2-input NAND gate and an inverter. However, this first conventional decoding circuit suffers disadvantages in that the distributing part requires multiple-input NAND gates and it is difficult to produce the decoding circuit having such a distributing part in the form of a semiconductor integrated circuit because of the large number of transistors required.
On the other hand, as will be described later in the present specification in conjunction with a drawing, a second conventional decoding circuit also comprises a decoding part and a distributing part. With respect to a 2-bit input code, for example, the decoding part also comprises four 2-input NAND gates, but the distributing part comprises four inverters and four transmission gates. According to this second conventional decoding circuit, the distributing part does not have multiple-input NAND gates. For this reason, the second conventional decoding circuit is more suited for production in the form of the semiconductor integrated circuit than the first conventional decoding circuit. However, as the number of bits of the input code increases, the construction and scale of the decoding circuit become extremely complex and large. Therefore, there is a demand to minimize the number of transistors required in the decoding circuit especially as the number of bits of the input code becomes large.
On the other hand, there are cases where the decoding logic of the decoding circuit needs to be changed. But according to the conventional decoding circuits, it is difficult and time consuming to modify the circuit construction of the decoding circuit so that the decoding logic is changed to a desired decoding logic, especially as the number of bits of the input code becomes large Hence, there is also a demand to realize a decoding circuit in which it is relatively simple to change the decoding logic.